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1 ? ISL84781 ultra low on-resistance, low-voltage, single supply, 8-to-1 analog multiplexer the intersil ISL84781 device contains precision, bidirectional, analog switches configured as an 8-channel multiplexer/demultiplexer. it is designed to operate from a single +1.6v to +3.6v supply. the device has an inhibit pin to simultaneously open all signal paths. on-resistance is 0.4 with a +3.0v supply and 0.55 with a single +1.8v supply. each switch can handle rail-to-rail analog signals. the off-leakage current is only 4na max at +25c or 40na max at +85c with a +3.3v supply. all digital inputs are 1.8v logic-compatible when using a single +3v supply. the ISL84781 is a 8-to-1 multiplexer device that is offered in a 16 ld tssop package, and a 16 ld thin qfn package. table 1 summarizes the performance of this family. related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? features ? pin compatible replacement for the max4781, and max4617 ? on-resistance (r on ) - v+ = +3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 ?r on matching between channels . . . . . . . . . . . . . . . . 0.12 ?r on flatness across signal range . . . . . . . . . . . . . . .0.056 ? single supply operation. . . . . . . . . . . . . . . . . +1.6v to +3.6v ? low power consumption (pd). . . . . . . . . . . . . . . . . . <0.2w ? fast switching action (v s = +3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns ? guaranteed break-before-make ? high current handling capacity (300ma continuous) ? available in 16 ld tssop and 16 ld 3x3 thin qfn ? 1.8v cmos-logic compatible (+3v supply) ? pb-free (rohs compliant) ? ISL84781ir replaces the isl43l680ir. applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio switching and routing table 1. features at a glance ISL84781 configuration 8:1 mux 3v r on 0.4 3v t on /t off 16ns/13ns 1.8v r on 0.55 1.8v t on /t off 24ns/16ns packages 16 ld tssop, 16 ld 3x3 thin qfn caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004, 2006, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. october 28, 2010 fn6095.4 data sheet
2 fn6095.4 october 28, 2010 pinouts (note 1) ISL84781 (16 ld tssop) top view ISL84781 (16 ld 3x3 thin qfn) top view note: 1. switches shown for logic ?0? inputs. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 no4 no6 com no7 no5 inh gnd n.c. v+ no1 no0 no3 add0 add1 add2 no2 logic 1 3 4 15 com no7 no5 inh no6 no4 v+ no2 16 14 13 2 12 10 9 11 6 578 no1 no0 no3 add0 n.c. gnd add2 add1 truth table ISL84781 inh add2 add1 add0 switch on 1 x x x none 0000no0 0001no1 0010no2 0011no3 0100no4 0101no5 0110no6 0111no7 note: logic ?0? 0.5v. logic ?1? 1.4v, with a 3v supply. x = don?t care. pin descriptions pin function v+ system power supply input (1.6v to 3.6v) n.c. no connect. not internally connected. gnd ground connection inh digital control input. connect to gnd for normal operation. connect to v+ to turn all switches off. com analog switch common pin no0 - no7 analog switch input pin add address input pin ordering information part number (notes 2, 3, 4) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL84781ivz 84781 ivz -40 to +85 16 ld tssop m16.173 ISL84781irz 781z -40 to +85 16 ld tqfn l16.3x3a 2. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 3. intersil pb-free products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020c. 4. for moisture sensitivity lev el (msl), please see device information page for ISL84781 . for more information on msl, please see technical brief tb363 . ISL84781
3 fn6095.4 october 28, 2010 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7v input voltages inh, no, add (note 5) . . . . . . . . . . . . . . . . . -0.3 to (v+) + 0.3v output voltages com (note 5) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (v+) + 0.3v continuous current no or com . . . . . . . . . . . . . . . . . . . . . 300ma peak current no or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . 500ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . >1000v thermal resistance (typical, note 6) ja (c/w) 16 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 150 16 ld 3x3 thin qfn package . . . . . . . . . . . . . . . . . 75 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. signals on no, com, add, or inh exceeding v+ or gnd are clamped by internal diodes. limit forward diode current to maximum cu rrent ratings. 6. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 3v supply test conditions: v supply = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 7), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 8, 11) typ max (notes 8, 11) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 2.7v, i com = 100ma, v no = 0 v to v+, (see figure 5) 25 - 0.41 0.75 full - - 0.8 r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no = voltage at max r on , (note 9) 25 - 0.12 0.2 full - - 0.2 r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no = 0 v to v+, (note 10) 25 - 0.056 0.15 full - - 0.15 no off leakage current, i no(off) v+ = 3.3v, v com = 0.3v, 3v, v no = 3v, 0.3v 25 -4 - 4 na full -40 - 40 na com on leakage current, i com(on) v+ = 3.3v, v com = v no = 0.3v, 3v 25 -15 - 15 na full -70 - 70 na digital input characteristics input voltage high, v inh , v addh full 1.4 --v input voltage low, v inl , v addl full - - 0.5 v input current, i inh , i inl , i addh , i addl v+ = 3.6v, v inh = v add = 0v or v+ (note 12) full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 2.7v, v no = 1.5 v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 16 25 ns full - - 27 ns inhibit turn-off time, t off v+ = 2.7v, v no = 1.5v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 14 23 ns full - - 25 ns address transition time, t trans v+ = 2.7v, v no = 1.5v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 19 28 ns full - - 30 ns break-before-make time, t bbm v+ = 3.3v, v no = 1.5v, r l = 50 , c l = 35pf, (see figure 3, note 12) 25 - 4 - ns full 1 --ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , (see figure 2) 25 - -39 - pc input off capacitance, c off f = 1mhz, v no = v com = 0v, (see figure 6) 25 - 65 - pf ISL84781
4 fn6095.4 october 28, 2010 com off capacitance, c off f = 1mhz, v no = v com = 0v, (see figure 6) 25 - 470 - pf com on capacitance, c com(on) f = 1mhz, v no = v com = 0v, (see figure 6) 25 - 485 - pf off-isolation r l = 50 , c l = 35pf, f = 100khz, (see figure 4) 25 - 65 - db total harmonic distortion (thd) f = 20hz to 20khz, 0.5v p-p , r l = 32 25 - 0.014 - % power supply characteristics power supply range full 1.6 - 3.6 v positive supply current, i+ v+ = 3.6v, v inh , v add = 0v or v+, switch on or off 25 - - 0.05 a full - - 1.2 a notes: 7. v in = input voltage to perform proper function. 8. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 9. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value. 10. flatness is defined as the difference between maximum and minimum value of on-re sistance over the specified analog signal ra nge. 11. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established b y characterization and are not production tested. 12. limits established by characterization and are not production tested. electrical specifications: 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v inh = 1v, v inl = 0.4v (note 7), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 8, 11) typ max (notes 8, 11) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 1.8v, i com = 10.0ma, v no = 1.0v, (see figure 5) 25 - 0.55 0.85 full - - 0.9 r on matching between channels, r on) v+ = 1.8v, i com = 10.0ma, v no = 1.0v, (see figure 5) 25 - 0.1 - full - 0.13 - r on flatness, r flat(on) v+ = 1.8v, i com = 10.0ma, v no = 0v, 0.9v, 1.6v, (see figure 5) 25 - 0.14 - full - 0.16 - digital input characteristics input voltage high, v inh , v addh full 1 -- v input voltage low, v inl , v addl full - - 0.4 v input current, i inh , i inl , i addh , i addl v+ = 1.8v, v inh , v add = 0v or v+ (note 12) full -0.5 - 0.5 a dynamic characteristics inhibit turn-on time, t on v+ = 1.8v, v no = 1.0v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 24 33 ns full - - 35 ns inhibit turn-off time, t off v+ = 1.8v, v no = 1.0v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 16 25 ns full - - 27 ns address transition time, t trans v+ = 1.8v, v no = 1.0v, r l = 50 , c l = 35pf, (see figure 1, note 12) 25 - 25 34 ns full - - 36 ns break-before-make time, t bbm v+ = 1.8v, v no = 1.0v, r l = 50 , c l = 35pf, (see figure 3, note 12) 25 - 9 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , (see figure 2) 25 - -20 - pc electrical specifications - 3v supply test conditions: v supply = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (note 7), unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 8, 11) typ max (notes 8, 11) units ISL84781
5 fn6095.4 october 28, 2010 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. inhibit t on /t off measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1b. inhibit t on /t off test circuit logic input waveform is inverted for switches that have the opposite logic sense. figure 1c. address t trans measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 1d. address t trans test circuit figure 1. switching times figure 2a. q measurement points figure 2b. q test circuit figure 2. charge injection 50% t r < 5ns t f < 5ns t on v+ 0v t off logic input switch output 90% 0v 90% v out vno0 v out v nox r l r l r on + ----------------------- - = logic input v out r l com no0 inh 50 35pf gnd no1-no7 c l vno0 add2-0 c v+ c 50% t r < 5ns t f < 5ns t trans 90% v+ vno7 0v t trans logic input switch output 10% v out 0v vno0 v out v nox r l r l r on + ----------------------- - = logic input v out r l com no0 add2-0 50 35pf gnd no1-no7 c l vno0 inh c v+ c v out v out off on off q = v out x c l switch output logic input v+ 0v c l v out r g v g gnd com nox logic input inh add2 v+ c repeat test for other switches. 1000pf 0 add1 add0 channel select ISL84781
6 fn6095.4 october 28, 2010 figure 3a. t bbm measurement points repeat test for other switches. c l includes fixture and stray capacitance. figure 3b. t bbm test circuit figure 3. break-before-make time figure 4. off-isolation test circuit figure 5. r on test circuit figure 6. capacitance test circuit test circuits and waveforms (continued) 90% v+ 0v t bbm logic input switch output 0v v out t r < 5ns t f < 5ns logic input add2-0 com r l c l v out 35pf 50 no0-no7 gnd vnox c inh v+ c analyzer r l signal generator 0v or v+ nox com add2 gnd inh 0v or v+ v+ 10nf add1 add0 channel select off-isolation is measured between com and ?off? no terminal on each switch. signal direction through switch is reversed and worst case values are recorded. 0v or v+ nox com add2 gnd v nx v 1 r on = v 1 /100ma 100ma inh v+ c add1 add0 channel select gnd nox com add2 impedance analyzer 0v or v+ inh v+ c add1 add0 channel select 1mhz ISL84781
7 fn6095.4 october 28, 2010 detailed description the ISL84781 analog multiplexer offers precise switching capability from a single 1.6v to 3.6v supply with ultra low on-resistance (0.41 ) and high speed operation (t on =16ns, t off = 13ns) with +3v supply. the device is especially well-suited for portable battery powered equipment thanks to the low operating supply voltage (1.6v), low power consumption (0.2w), and low leakage currents (70na max). high frequency applicat ions also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 7). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 7). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not applicable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see figure 7). these additional diodes limit the analog signal from 1v below v+ to 1v above gnd. the low leak age current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. power-supply considerations the ISL84781 construction is ty pical of most single supply cmos analog multiplexers, in that it has two supply pins: v+ and gnd. v+ and gnd drive t he internal cmos switches and set its analog voltage limits. unlike switches with a 4v maximum supply voltage, the ISL84781 4.7v maximum supply voltage provides plenty of room for the 10% tolerance of 3.6v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.6v but the part will operate with a supply be low 1.5v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the electrical specification t ables and ?typical performance curves? beginning on page 8 for details. v+ and gnd power the internal logic and level shifters. the level shifters convert the logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. these multiplexers cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. logic-level thresholds this device is 1.8v cmos comp atible (0.5v and 1.4v) over a supply range of 2.0v to 3.6v (see figure 12). at 3.6v the v ih level is about 1.27v. this is still below the 1.8v cmos guaranteed high output minimum level of 1.4v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 systems, signal response is reasonably flat even past 10mhz with a -3db bandwidth of 52mhz (see figure 16). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch?s input to its output. off-isolation is the resistance to this feed-through. figure 17 details the high off isolation provided by these devi ces. at 100khz, off isolation is about 65db in 50 systems, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. figure 7. overvoltage protection gnd v com v nox optional protection v+ logic diode optional protection diode optional protection resistor for logic inputs 1k ISL84781
8 fn6095.4 october 28, 2010 virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and t herefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog- signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage curren ts of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. typical performance curves t a = +25c, unless otherwise specified figure 8. on-resistance vs supply voltage vs switch voltage figure 9. on-resistance vs switch voltage figure 10. on-resistance vs switch voltage figure 11. charge injection vs switch voltage 01234 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 r on ( ) v com (v) i com = 100ma v+ = 3v v+ = 2.7v v+ = 1.8v v+ = 3.6v v+ = 1.65v 0.30 0.35 0.40 0.45 0.50 0.55 r on ( ) v com (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 +25c +85c -40c v+ = 3v i com = 100ma 0 0.5 1.0 1.5 2.0 r on ( ) v com (v) 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 +85 c -40 c +25 c v+ = 1.8v i com = 100ma 0 0.5 1.0 1.5 2.0 2.5 3.0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 q (pc) v com (v) v+ = 1.8v v+ = 3v ISL84781
9 fn6095.4 october 28, 2010 die characteristics substrate potential (powered up): gnd (qfn paddle connection: to ground or float) transistor count: 228 process: submicron cmos figure 12. digital switching point vs supply voltage figure 13. address trans time vs supply voltage figure 14. inhibit turn-on time vs supply voltage figure 15. inhibit turn-off time vs supply voltage figure 16. frequency respons e figure 17. off-isolation typical performance curves t a = +25c, unless otherwise specified (continued) 0.6 0.8 1.0 1.2 1.4 1.6 v+ (v) v inh and v inl (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v inh v inl t rans (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10 20 30 40 50 60 +25c +85c -40c t on (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 10 20 30 40 50 60 +85c -40c +25c t off (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40c 10 15 20 25 +85c +25c frequency (mhz) 0 -10 normalized gain (db) gain phase v+ = 3v 0 20 40 60 80 100 phase () 0.1 1 10 100 v in = 0.2v p-p to 2v p-p r l = 50 frequency (hz) 1k 100k 1m 100m 500m 10k 10m -100 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation v+ = 3v ISL84781
10 fn6095.4 october 28, 2010 ISL84781 package outline drawing m16.173 16 lead thin shrink small outline package (tssop) rev 2, 5/10 0.09-0.20 see detail "x" detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. (0.65 typ) (5.65) (0.35 typ) 0.90 +0.15/-0.10 0.60 0.15 0.15 max 0.05 min plane gauge 0-8 0.25 1.00 ref (1.45) 16 2 1 3 8 b 1 3 9 a pin #1 i.d. mark 5.00 0.10 6.40 4.40 0.10 0.65 1.20 max seating plane 0.25 +0.05/-0.06 5 c h 0.20 c b a 0.10 c - 0.05 0.10 c b a m
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6095.4 october 28, 2010 ISL84781 thin quad flat no-lead plastic package (tqfn) thin micro lead frame pl astic package (tmlfp) ) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l16.3x3a 16 lead thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a2 - - 0.80 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 1.35 1.50 1.65 7, 8, 10 e 3.00 bsc - e1 2.75 bsc 9 e2 1.35 1.50 1.65 7, 8, 10 e 0.50 bsc - k0.20 - - - l 0.30 0.40 0.50 8 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 0 6/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. compliant to jedec mo-220weed-2 issue c, except for the e2 and d2 max dimension.

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